Comprehensive RTOS simulator with interrupt-driven architecture, priority-based scheduling, and bounded latency guarantees
Modern automotive systems require real-time processing of critical sensor data where delayed responses can lead to catastrophic failures, accidents, and loss of life. Traditional general-purpose operating systems cannot guarantee bounded response times, deterministic behavior, or priority-based preemption necessary for safety-critical vehicle operations such as emergency braking, collision avoidance, and speed regulation. Existing vehicle control systems often lack proper task prioritization, suffer from unpredictable latencies, face race conditions in shared resource access, and provide inadequate visibility into system behavior for debugging and verification.
There is a critical need for a Real-Time Operating System (RTOS) that can handle multiple concurrent sensor inputs with guaranteed response times, prioritize safety-critical tasks, prevent resource conflicts, and provide deterministic execution patterns. This project addresses these challenges by developing a comprehensive RTOS simulator that implements interrupt-driven architecture with microsecond-precision timing, priority-based preemptive scheduling for brake (P7), collision (P6), and speed (P5) sensors, mutex-protected shared resources to prevent race conditions, and complete event logging with bounded latency guarantees (<5μs interrupt response), enabling automotive engineers and embedded systems developers to design, test, and verify real-time vehicle safety systems in a controlled environment.
The system implements a complete Real-Time Operating System simulator built with Python and Flask, featuring an interrupt controller that manages virtual hardware interrupts, ISR (Interrupt Service Routine) handlers that respond within 5μs, and a preemptive priority scheduler that manages three sensor tasks with priorities 7 (Brake-critical), 6 (Collision-high), and 5 (Speed-medium). The architecture ensures higher priority tasks always preempt lower priority ones, guaranteeing deterministic behavior and bounded worst-case execution times (WCET).
The interrupt controller simulates hardware-level interrupt generation with microsecond timestamp precision. Each sensor event triggers an ISR that performs minimal processing (logging entry/exit, signaling tasks) before returning control, deferring actual work to corresponding tasks. The priority queue ensures interrupts are processed in strict priority order, preventing lower-priority interrupts from blocking critical ones. Shared resources including sensor readings and system state are protected with mutexes implementing priority inheritance to prevent priority inversion and deadlock scenarios.
A real-time web dashboard built with HTML5, CSS3, and JavaScript provides live monitoring of all system components. The interface features sensor event simulators for triggering virtual hardware interrupts, real-time status cards displaying current sensor readings and task states, comprehensive system statistics showing CPU usage and task counts, and a detailed event log with microsecond-precision timestamps capturing all interrupts, ISR entries/exits, task preemptions, and resource access events with export functionality for analysis.